Ultralow-power SRAM technology
نویسندگان
چکیده
An ultralow-standby-power technology has been developed in both 0.18m and 0.13m lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage sixtransistor (6T) SRAM cell sizes are 4.81 m and 2.34 m, corresponding respectively to the 0.18m and 0.13m design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25 C and is less than 400 fA per cell at 1.5 V, 85 C. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the wellknown gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.
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عنوان ژورنال:
- IBM Journal of Research and Development
دوره 47 شماره
صفحات -
تاریخ انتشار 2003